The performance of computer systems, especially personal computers, has improved dramatically due to the rapid growth in computer architecture design, and in particular, to the performance of computer memory. The speed with which a processor can access data is critical to its performance, while providing uniformly fast memory access can be cost prohibitive. To get around this problem, computer architectures have relied on a mix of fast, less dense, memory and slower bulk memory. In fact, many computer architectures have a multilevel memory architecture in which an attempt is made to find information in the fastest memory. If the information is not in that memory, a check is made at the next fastest memory. This process continues down through the memory hierarchy until the information sought is found. One critical component in such a memory hierarchy is a cache memory.
Cache memories rely on the principle of locality to attempt to increase the likelihood that a processor will find the information it is looking for in the cache memory. To do this, cache memories typically store contiguous blocks of data. In addition, the cache memory stores a tag which is compared to an address to determine whether the information the processor is seeking is present in the cache memory. Cache memories are usually constructed from higher speed memory devices such as static random access memory (SRAM). The typical cache memory transfers a cache line as a contiguous block of data, starting at the first word in the cache line and proceeding through to the last. Each of the bits of a cache line is typically stored in a different memory array block using one write operation. As such, numerous blocks of memory must be accessed for writing a line of data.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an SRAM which can store a line of data in a single memory array block while maintaining a minimum number of input data lines.